Seeed Arch Link 板子介紹

Seeed Arch Link

Arch Link is an mbed enabled development board based on Nordic nRF51822 and WIZnet W5500 ethernet interface. With Arduino form factor, Grove connectors and micro SD interface, it is extremely easy to create a bluetooth low energy device.

Features

• mbed enabled
  • Online IDE
  • Easy to use C/C++ SDK
  • Handy libraries
• CMSIS DAP based on LPC11U35
  
  • Drag-n-drop programming
  • Debug using CMSIS DAP standard
  • USB virtual serial for communication
• Arduino form factor with Grove connectors
  • I2C and UART connecter on board
• Nordic nRF51822 Multi-protocol Bluetooth® 4.0 low energy/2.4GHz RF SoC
  • ARM Cortex M0 processor
  • 256kB flash/16kB RAM
  • Configurable I/O mapping for digital I/O
• WIZnet W5500 Ethernet
  • Supports following Hardwired TCP/IP Protocols : TCP, UDP, ICMP, IPv4, ARP, IGMP, PPPoE
  • Supports Power down mode
  • Supports Wake on LAN over UDP
  • Supports High Speed Serial Peripheral Interface(SPI MODE 0, 3)
  • Internal 32Kbytes Memory for Tx/Rx Buffers
  • 10BaseT/100BaseTX Ethernet PHY embedded
  • with RJ45 connector
• USB Micro B connector
• Micro SD Card connector

主晶片: NXP''s LPC11U35FHI33: 

Scalable Entry Level 32-bit Microcontroller (MCU) based on ARM® Cortex®-M0+/M0 Cores

Features

• ARM Cortex-M0 processor, running at frequencies of up to 50 MHz
• ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC)
• Non Maskable Interrupt (NMI) input selectable from several input sources
• System tick timer
• 64 kB on-chip flash program memory
• 4 kB on-chip EEPROM data memory
• 12 kB SRAM data memory
• 16 kB boot ROM
• In-System Programming (ISP) and In-Application Programming (IAP)
• ROM-based USB drivers. Flash updates via USB supported
• ROM-based 32-bit integer division routines
• Standard JTAG (Joint Test Action Group) test interface
• Serial Wire Debug
• 26 General Purpose I/O (GPIO) pins
• Up to 8 GPIO pins can be selected as edge and level sensitive interrupt sources
• Two GPIO grouped interrupt modules enable an interrupt
• High-current source output driver (20 mA) on one pin
• High-current sink driver (20 mA) on true open-drain pins
• Four general purpose counter/timers
• Programmable Windowed WatchDog Timer (WWDT)
• 10-bit ADC with input multiplexing among eight pins
• USB 2.0 full-speed device controller
• USART with fractional baud rate generation
• Two SSP controllers with FIFO and multi-protocol capabilities -->SPIx2
• I2C-bus interface supporting the full I2C-bus specification and Fast-mode Plus
• Crystal Oscillator with an operating range of 1 MHz to 25 MHz (system oscillator)
• 12 MHz high-frequency Internal RC oscillator (IRC)
• Internal low-power, low-frequency WatchDog Oscillator (WDO)
• PLL allows CPU operation up to the maximum CPU rate
• A second, dedicated PLL is provided for USB
• Clock output function with divider
• Integrated PMU (Power Management Unit)
• Power profiles residing in boot ROM provide optimized performance
• Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down
• Processor wake-up from Deep-sleep and Power-down modes
• Processor wake-up from Deep power-down mode using one special function pin
• Power-On Reset (POR)
• Brownout detect with four separate thresholds for interrupt and forced reset
• Unique device serial number for identification
• Single 3.3 V power supply (1.8 V to 3.6 V)
• Temperature range −40 °C to +85 °C

資料下載:

• NXP' s LPC11U35FHI33