IT Lab艾鍗學院技術Blog: Raspberry Pi mini UART

mini UART 規格如下:

The mini Uart has the following features:
• 7 or 8 bit operation.
• 1 start and 1 stop bit.
• No parities.
• Break generation.
• 8 symbols deep FIFOs for receive and transmit.
• SW controlled RTS, SW readable CTS.
• Auto flow control with programmable FIFO level.
• 16550 like registers.
• Baudrate derived from system clock.

mini UART 暫存器控制整理如下:

AUX BaseAddr 0x7E210000

0x7E21 5000 AUX_IRQ Auxiliary Interrupt status
0x7E21 5004 AUX_ENABLES Auxiliary enables
0x7E21 5040 AUX_MU_IO_REG Mini Uart I/O Data
0x7E21 5044 AUX_MU_IER_REG Mini Uart Interrupt Enable
0x7E21 5048 AUX_MU_IIR_REG Mini Uart Interrupt Identify
0x7E21 504C AUX_MU_LCR_REG Mini Uart Line Control
0x7E21 5050 AUX_MU_MCR_REG Mini Uart Modem Control
0x7E21 5054 AUX_MU_LSR_REG Mini Uart Line Status
0x7E21 5058 AUX_MU_MSR_REG Mini Uart Modem Status
0x7E21 505C AUX_MU_SCRATCH Mini Uart Scratch
0x7E21 5060 AUX_MU_CNTL_REG Mini Uart Extra Control
0x7E21 5064 AUX_MU_STAT_REG Mini Uart Status
0x7E21 5068 AUX_MU_BAUD_REG Mini UART Baud Rate

AUXIRQ : the mini UART has an interrupt pending if bit 0 is set
AUXENB : used to enable miniUART function
AUX_MU_CNTL_REG : used to enable RX & TX operation on miniUART
AUX_MU_IO_REG : used to write data (1 byte) to and read data (1 byte) from the RX/TX FIFO (8 byte buffer).
AUX_MU_IER_REG: used to enable interrupts and to clear RX/TX FIFO
AUX_MU_IIR_REG: used to identify/determine TX or RX interrupt and to clear interrupt pending bit
AUX_MU_LCR_REG : used to set data bit length (8 bit or 7 bit) and gives access to the baudrate register (DLAB access=1)
AUX_MU_BAUD : set the 16-bit wide baudrate counter.
AUX_MU_STAT_REG: Some information about the internal status of the miniUART.
bit[27:24] Transmit FIFO fill level: TX FIFO有多少資料 (範圍:0~8 byte)
bit[19:16] Receive FIFO fill level : RX FIFO有多少資料 (範圍:0~8 byte)

Note:

AUXENB : If the enable bits are clear you will have no access to a peripheral. You can not even read or write the registers!
GPIO pins should be set up first the before enabling the UART. So when it is enabled any data at the inputs will immediately be received . If the UART1_RX line is low (because the GPIO pins have not been set-up yet) that will be seen as a start bit and the UART will start receiving 0x00-characters.
After a reset: the baudrate will be zero and the system clock will be 250 MHz
Baud Rate:

Figure 2. UART receive frame synchronization and data sampling points.

Figure shows a common method used by a UART receiver to synchronize itself to a received frame. The receive UART uses a clock that is 16 times the data rate. A new frame is recognized by the falling edge at the beginning of the active-low START bit. This occurs when the signal changes from the active-high STOP bit or bus idle condition. The receive UART resets its counters on this falling edge, expects the mid-START bit to occur after 8 clock cycles, and anticipates the midpoint of each subsequent bit to appear every 16 clock cycles thereafter. The START bit is typically sampled at the middle of bit time to check that the level is still low and ensure that the detected falling edge was a START bit, not a noise spike. Another improvement is to sample the START bit three times (clock counts 7, 8, and 9, out of 16) instead of sampling it only at the midbit position (clock count 8 out of 16).

BCM2835設定BaudRate counter兩種方式

void rpi_aux_mu_init() {
volatile uint32_t reg_val;
uint32_t t;

/* Enable aux uart */
RPI_AUX->ENABLES = RPI_AUX_MU_ENABLE;

RPI_AUX->MU_IER = 0;

/* Disable flow control */
RPI_AUX->MU_CNTL = 0;

RPI_AUX->MU_LCR = RPI_AUX_MU_LCR_8BIT_MODE;

RPI_AUX->MU_MCR = 0;

/* Diable all interrupts from mu and clear the fifos */
RPI_AUX->MU_IER = 0;
RPI_AUX->MU_IIR = 0xC6;

//#define bits 8
//RPI_AUX->MU_BAUD = ( _RPI_SYS_FREQ / ( 8 * bits )) - 1;
RPI_AUX->MU_BAUD = 270;

/* Setup GPIO 14 and 15 as alternative function 5 which is
UART 1 TXD/RXD. These need to be set before enabling the UART */

reg_val = memio_read32(_GPIO_FSEL1);
reg_val &= ~(7 << 12); // GPIO 14
reg_val |= 2 << 12; // ALT5
reg_val &= ~(7 << 15); // GPIO 15
reg_val |= 2 << 15; // ALT5

memio_write32(_GPIO_FSEL1, reg_val);
memio_write32(_GPIO_PUD, 0);
dummy(150);
memio_write32(_GPIO_PUD_CLK0, (1 << 14) | (1 << 15));
dummy(150);
memio_write32(_GPIO_PUD_CLK0, 0);

RPI_AUX->MU_CNTL = RPI_AUX_MU_CNTL_TX_ENABLE | RPI_AUX_MU_CNTL_RX_ENABLE;
}